The present invention relates to the memory macro test circuit of a memory-embedded LSI and, more particularly, to a memory-embedded LSI on which a plurality of memory macros are laid out in one chip.
In recent years, a great deal of attention is paid to a so-called memory-embedded LSI (system LSI) on which a plurality of functions including a semiconductor memory function (memory macro) are integrated on one chip to form a specific system within the chip. In the memory-embedded LSI, the semiconductor memory function and logic function, which have been formed on separate chips, are formed on one chip to contribute to high system performance, low power consumption, and downsizing (small number of components).
The memory macro contains all circuits necessary for the operation of the semiconductor memory, and can internally complete a series of operations such as a read and write. The memory macro contains an interface serving as a contact between the memory macro and logic section to directly exchange data between them.
The memory macro of the memory-embedded LSI incorporates a test control block in order to confirm the function of the memory macro. In a test, this test control block functions to test the memory macro. However, in a memory-embedded LSI having a plurality of memory macros, these memory macros are tested one by one to spend a long test time. Separately testing a plurality of memory macros requires a circuit for identifying these memory macros, so that the layout of the test control block in each memory macro changes. The test control block must be designed for every memory macro, resulting in a long memory macro design time.
The present invention has been made to overcome the conventional drawbacks, and has as its object to provide a memory-embedded LSI capable of easily testing a memory macro within a short time and designing the memory macro within a short time in a memory-embedded LSI having a plurality of memory macros.
1) According to the present invention, a memory-embedded LSI comprises a plurality of memory macros which are laid out in one chip and have a semiconductor memory function, macro ID generation circuits arranged outside the plurality of memory macros in the one chip to generate macro IDs for identifying the plurality of memory macros, and an output selection circuit arranged outside the plurality of memory macros in the one chip to electrically connect one of the plurality of memory macros to an output pad.
The output pad outputs an output signal from each memory macro in a test.
The memory-embedded LSI according to the present invention further comprises macro selection circuits each for selecting one of the plurality of memory macros on the basis of the macro ID.
The macro selection circuits are arranged in the memory macros and have the same layout between the memory macros. The macro selection circuits may be arranged outside the plurality of memory macros together with the macro ID generation circuits.
The macro ID generation circuits generate the macro IDs using a combination of a plurality of fixed potentials.
2) According to the present invention, a memory-embedded LSI comprises a plurality of memory macros which are laid out in one chip and have a semiconductor memory function, a plurality of adders which are arranged in correspondence with the plurality of memory macros and have a function of adding input signals and generating output signals, and an output selection circuit arranged outside the plurality of memory macros in the one chip to electrically connect one of the plurality of memory macros to an output pad, wherein the plurality of adders are series-connected to each other, and input or output signals of the plurality of adders are used as macro IDs for identifying the plurality of memory macros.
The plurality of adders are arranged in corresponding memory macros and have the same layout between the memory macros.
3) According to the present invention, a memory-embedded LSI comprises a plurality of memory macros which are laid out in one chip and have a semiconductor memory function, macro selection circuits each for selecting one of the plurality of memory macros, a plurality of macro output control circuits which are arranged in correspondence with the plurality of memory macros and have a function of setting an output signal from an unselected memory macro to a fixed potential, and a logic circuit arranged outside the plurality of memory macros in the one chip to guide only an output signal from a selected memory macro to an output pad by performing logic processing for output signals from the plurality of memory macros.
The plurality of macro output control circuits are arranged in corresponding memory macros and have the same layout between the memory macros.
The logic circuit executes OR logic or AND logic of output signals from the plurality of memory macros.
4) According to the present invention, a memory-embedded LSI comprises a plurality of memory macros which are laid out in one chip and have a semiconductor memory function, macro selection circuits each having a function of selecting at least two of the plurality of memory macros, and a logic circuit arranged outside the plurality of memory macros in one chip to generate a PASS/FAIL bit representing whether the output signals from at least the two selected memory macros coincide with each other by performing logic processing for output signals from at least the two selected memory macros.
When the output signals from at least two selected memory macros coincide with each other, the logic circuit outputs the output signals from at least the two selected memory macros to an output pad.
5) According to the present invention, a memory macro outputting n-bit data comprises a circuit for reading out j (j is a natural number of not less than 2) sets of s-bit (1xe2x89xa6sxe2x89xa6n) data to compare the s-bit data between the sets, and outputting a PASS/FAIL bit representing whether the s-bit data of the sets coincide with each other.
When the s-bit data of the sets coincide with each other, the circuit outputs the s-bit data of the sets outside the memory macro.
6) In the memory-embedded LSI according to the present invention, each memory macro in the memory-embedded LSI of 4) comprises the circuit of 5). 7) According to the present invention, a memory macro outputting n-bit data comprises a circuit for reading out s-bit (1xe2x89xa6sxe2x89xa6n) data to compare the s-bit data with an expected value for determining whether the s-bit data is correct, and outputting a PASS/FAIL bit representing whether the s-bit data coincides with the expected value.
According to the present invention, a memory macro outputting n-bit data comprises a circuit for reading out j (j is a natural number of not less than 2) sets of s-bit (1xe2x89xa6sxe2x89xa6n) data to compare the s-bit data between the sets and compare the s-bit data of each set with an expected value for determining whether the s-bit data is correct, and outputting a PASS/FAIL bit representing whether the s-bit data of the sets coincide with each other and whether the s-bit data of each set coincides with the expected value.
8) According to the present invention, a test method for testing a plurality of memory macros in one chip comprises the steps of simultaneously selecting the plurality of memory macros to write the same data in the memory macros, outputting a PASS/FAIL bit representing whether output signals from the memory macros coincide with each other to output, when the output signals from the memory macros coincide with each other, the output signals from the memory macros, and determining nondefectives/defectives of the plurality of memory macros on the basis of the PASS/FAIL bit and the output signals from the memory macros.
According to the present invention, a test method for testing a memory macro outputting n-bit data comprises the steps of assuming j (j is a natural number of not less than 2) blocks in units of s bits (1xe2x89xa6sxe2x89xa6n) in the memory macro to write the same data in the blocks, outputting a PASS/FAIL bit representing whether s-bit output signals from the blocks coincide with each other to output, when the s-bit output signals from the blocks coincide with each other, the s-bit output signals from the blocks, and determining nondefectives/defectives of the memory macro on the basis of the PASS/FAIL bit and the s-bit output signals from the blocks.
According to the present invention, a test method for testing a plurality of memory macros, each outputting n-bit data comprises the steps of assuming j (j is a natural number of not less than 2) blocks in units of s bits (1xe2x89xa6sxe2x89xa6n) in each memory macro to write the same data in the blocks, outputting a PASS/FAIL bit representing whether s-bit output signals from the blocks coincide with each other and whether output signals from the memory macros coincide with each other, when the s-bit output signals from the blocks coincide with each other and the output signals from the memory macros coincide with each other, outputting the output signals from the memory macros, and determining nondefectives/defectives of the plurality of memory macros on the basis of the PASS/FAIL bit and the output signals from the memory macros.
According to the present invention, a test method for testing a memory macro outputting n-bit data comprises the steps of reading out s-bit ((1xe2x89xa6sxe2x89xa6n) data of the memory macro, comparing the s-bit data with an expected value for determining whether the s-bit data is correct in the memory macro, generating a PASS/FAIL bit representing whether the s-bit data coincides with the expected value, and determining nondefectives/defectives of the memory macro on the basis of the PASS/FAIL bit.
According to the present invention, a test method for testing a memory macro outputting n-bit data comprises the steps of assuming j (j is a natural number of not less than 2) blocks in units of s bits (1xe2x89xa6sxe2x89xa6n) in the memory macro to read out s-bit (1xe2x89xa6sxe2x89xa6n) data of the blocks, comparing the s-bit data of the blocks with each other in the memory macro while comparing the s-bit data of each block with an expected value, thereby generating a PASS/FAIL bit representing whether the s-bit data of the blocks coincide with each other and whether the s-bit data of each block coincides with the expected value, and determining nondefectives/defectives of the memory macro on the basis of the PASS/FAIL bit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.